1. Field
Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a nonvolatile memory device and a method for fabricating the same.
2. Description of the Related Art
In order to realize high integration, a NAND flash memory, which is a nonvolatile memory device, includes a plurality of cells, which are coupled in series to form a unit string. NAND flash memories are capable of substituting a memory stick, a USB driver, and a hard disk.
During a fabrication process of the NAND flash memory, a self aligned-shallow trench isolation (SA-STI) process or advanced self aligned-shallow trench isolation (ASA-STI) process is applied to realize element isolation and form a floating gate.
FIG. 1 is a diagram illustrating a conventional nonvolatile memory device.
Referring to FIG. 1, a plurality of active regions 13 isolated by a plurality of trenches 12 are formed in a substrate 11. A tunnel isolation layer 14 is formed on each of the active regions 13, and a floating gate 15 is formed on the tunnel isolation layer 14. An isolation layer 16 is buried in each of the trenches 12, and the upper surface of the isolation layer 16 is positioned lower than the upper surface of the floating gate 15. A dielectric layer 17 is formed on the entire surface of the resultant structure including the floating gate 15 and the isolation layer 16. The dielectric layer 17 has an oxide-nitride-oxide (ONO) structure including an oxide 17A, a nitride 17B, and an oxide 17C. A control gate 18 is formed on the dielectric layer 17.
In FIG. 1, the plurality of trenches 12 for isolating the plurality of active regions 13 are spaced at even intervals from each other. The floating gate 15 has both sidewalls contacted with the dielectric layer 17, and the control gate 18 is formed over the dielectric layer 17 both above and between the floating gates 15.
As the NAND flash memory is highly integrated, a 20-nm class NAND flash memory may employ symmetrical floating gates. More specifically, as illustrated in FIG. 1, spaces S1 to S3 are equal to each other (S1=S2=S3), and both sidewalls of the floating gate 16 contact the dielectric layer 17.
In the conventional nonvolatile memory device, however, since the space between the floating gates 15 is small, securing a physical space where the control gate 18 is to be formed after the dielectric layer 17 is deposited is difficult.
To secure the physical space for the control gate 18, the critical dimension (CD) of the active region 13 may be reduced to increase the CD of the trench 12 and the space between the floating gates 15. However, since the spaces between the respective floating gates 15 are equal in size, it is not easy to secure the physical space. Therefore, using the floating gate 15 may be limited.